The present invention relates generally to a method for reducing chemo-epitaxy Directed Self-Assembly (DSA) defects, and more particularly, but not by way of limitation, to a method and recording medium of reducing the Directed Self Assembly (DSA) defects formed at a boundary of a circuit block as well as across a large gap between two groups of close pitch lines due to a chemo-epitaxy DSA process.
The directed self-assembly (DSA) of block co-polymers (BCPs) is a promising technology to extend patterning resolution. Chemo-epitaxy, a form of DSA, has been demonstrated to reliably generate dense grating and hexagonal arrays from sparse chemical pre-patterns comprising a directing (pinning) region and a non-directing (neutral) region that support perpendicular orientation of BCP domains. Typically, the directing region confers alignment on the BCP domains via a preferential affinity to one of the domains. The neutral region may have little or no affinity to any of the domains.
Some conventional techniques describe a guiding pattern mask decomposition method specific for Chemoepitaxy DSA process. The conventional techniques includes the use of internal dummy guiding (neutral) patterns.
However, the conventional techniques have a technical problem in that the conventional techniques do not consider an issue of how to design internal dummy guiding patterns optimally. Further, the conventional techniques do not consider the use of external dummy features which are critical and the proper way to design them to reduce DSA defects formed near the edge of the circuit block. Further, the conventional techniques do not include the external dummy patterns together with the usual global fill patterns for a chemoepitaxy process.
That is, a chemoepitaxy DSA process requires a restricted set of pattern periodicity and dimensions to make sure DSA is commensurable (i.e., phase segregation) without defect formation. However in real VLSI circuit design, the patterns are in general not fixed gratings. The guiding patterns derived from the design have various quantized widths and spacing. Defects tend to form when the spacing between guiding patterns is larger than a set value. The pattern at the boundary of a cell block will see a large empty area as opposed to the interior of the block. The large empty area will be a source of defects too. The inventors aim to solve the defects problem by special dummy guiding patterns insertion, internal and external, in a Fin Field Effect Transistor (FinFET) integrated circuits design.
Thus, there is a problem in the art that in the conventional techniques, DSA defects form near the edge of the circuit patterns if a properly designed dummy patterns there around is not formed.